Verilog HDL: Behavioural Modeling: 8-Bit Ring Counter, 8-Bit Adder

8-Bit Ring Counter

Use concatenation operator:

xn={x[2:0],x[0]}

for n bit, xn={x[n-1:0],1’b0}

always @ (posedge reset or posedge clk)

if (reset == 1’b1)

count = 8’b0000_0001;

else if (enable==1’b1)

count={count[6:0],count[7]};     //shift using concatenation operator

 

module clockgen;

reg clk;

initial clk=1’b0;

forever

#20 clk= ~clk;

initial #500 $stop;

endmodule

//$stop à stops and puts execution o interactive mode; Either you can ‘halt’ or ‘procedd’

//$finish à terminates the simulation itself

//time unit can be changed by setting in simulator or you can change using compiler directive called ‘timescale’

Behavioural 8-Bit Adder:

module adder8bit (sum, carry, a, b, cin)

input [7:0] a,b;

output [7:0] sum; reg [7:0] sum;

output carryout ; reg carryout;

reg [8:0] c;

always

begin

c[1]=cin;

for (i=0; i<7; i=i+1)

{c[i+1],s[i]=a[i]+b[i]+c[1];

endloop

cr=c[8];

end

endmodule